AXI Protocol and VIP Development Training

About Course

AMBA Protocol training is structured to enable engineers gain perfection in AXI, AHB & APB protocols. Majority of designs are based on ARM architecture. All ARM architectures are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have detailed understanding of these protocols. SoC design debug and testbench component coding in most cases involves either AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.

... AMBA Protocol training course focuses on teaching protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB2.0 and APB. Course also focus on teaching protocol testbench development concepts. Student has flexibility to choose specific protocol as well.


Introduction to on-chip protocols
Protocol overview
AXI revisions
AXI based system architecture
Global signals
Write address channel signals
Write data channel signals
Write response channel signals
Read address channel signals
Read data channel signals
Low power interface signals
Basic write and read transactions
Relationship between channels
Transaction structure
Transaction types and attributes
AXI3 memory attribute signalling
AXI4 changes to memory attribute signalling
Memory types
Mismatched memory attributes
Transaction buffering
Access permissions
AXI transaction identifiers
Transaction ID
Transaction ordering
Definition of ordering model
Master ordering
Interconnect ordering
Slave ordering
Response before final destination
Single-copy atomicity size
Exclusive accesses
Locked accesses
Atomic access signaling
QoS signaling
Multiple region signaling
User-defined signaling
Low power interface signals
Low power clock control
Interoperability principles
Major Interface categories
Default signal values
VIP architecture
VIP components
VIP types
Master, Slave
Active, Passive
VIP test scenario listing down
VIP component coding
Driver, Generator, Monitor, Coverage, Environment
Interface, transaction, Slave model, assertions
Testbench integration
Testcase coding
Simulations and waveform analysis
Functional coverage analysis
Assertion coding and analysis
Enhance AXI3 VIP for AXI4 additional features
QoS signaling
Multiple region signaling
User-defined signaling
Low power interface

Course videos

Lecture 1 AXI Protocol overview and features 03:26:12
Lecture 2 AXI channels, signal encoding, timing diagrams 01:49:06
Lecture 3 AXI protocol advanced features 01:42:21
Lecture 4 AXI protocol advanced features 01:05:55
Lecture 5 AXI VIP Development 04:07:08
Lecture 6 AXI VIP Development 04:07:08
Lecture 7 AXI advanced feature checking 00:25:08
Lecture 8 AXI UVC(UVM based) Development 01:08:08
Lecture 9 AXI Interview questions 00:26:08
Lecture 10 AXI interconnect development concepts 00:06:08
Lecture 11 AXI UVC bringup 00:03:12

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