About Course

DFT(Design for Testability) involves using SCAN, ATPG, JTAG and BIST techniques to add testability to the Hardware design. These techniques are targeted for developing and applying tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, and transition delay faults etc.

DFT Training will focus on all aspects of testability flow including DFT basics,  various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.

... As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests. ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.
DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG, JTAG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression, JTAG and ATPG pattern generation using Tessent tool. More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.
MentorGraphics Tessent tool is used for training. As per industry survey, it is used by more than 80% companies for DFT. Student will have access to tool at the institute for 12 months after course completion, with a provision to extend beyond.


ASIC & VLSI Design Flow
Session covering complete flow overview from product requirements to Post silicon validation.
Advanced Digital Design
2 weeks dedicated course focusing on all aspects of Digital design.
Verilog programming basics
3 Weeks of Verilog training covering all the aspects of Verilog required for DFT engineer
This course is done in parallel with Advanced Digital design course
Linux OS
1 week training on Linux OS and hands on
TCL Scripting
1 week training on TCL scripting for flow automation
DFT Basics
SoC Scan architecture overview
Types of Scan
ATPG Simulation Mismatch Debug
DFT Diagnosis
Scan and ATPG
Test compression technigues
Hierarchical Scan Design
Full SOC flow - DFT
DFT Architecture and Basics
Test Plan
Different DFT schemes
Comparison between Functional and DFT Vectors
Understanding of SCAN Insertion
Scan methodology
Types of Scan
Top-down and Bottom-up Approach
Scan insertion Flow
Scan insertion Scripts
Multiple Clock domains
Design Rule Checking
Pre-DRC and Post DRC
Lock up and Terminal lockup latches
Hands-on Scan insertion
Introduction to compression
Compression Architecture
Decompressor and Compactor
Compression Ratio
DRC Analysis
Modular Compression
X-Masking logic
Hands-on Compression
Scan insertion with compression
On-chip clocking for at-speed testing
Hierarchical Scan Design
Bypass mode
Hands on Scan and compression
Interaction session scan and compression
Memory faults
Diagnostic mode
Memory faults
Diagnostic mode
MBIST Hands on project
ATPG Overview
Different types of Faults
Types of fault models
ATPG Overview
Different types of Faults
Types of fault models
ATPG algorithm
Understand complete Test procedure
Hands on Project
DRC analysis
Test Coverage and Fault Coverage
Coverage improvement Analysis
Chain and Capture patterns
Simulations- No-timing and Timing simulations
At speed fault model (In detail)
Understanding Transition fault ATPG
Two pulse generator
Test procedure
Launch on capture and Launch on Shift
Top-off Pattern generation
Path delay
Introduction to JTAG
JTAG State Machine
Boundary Scan
Different instructions
Industry Standard Project
Introduction to LBIST
Mock Interview

Course videos

Lecture 1 VLSI Design flow Session1 02:52:37
Lecture 2 VLSI Design flow Session2 02:01:39
Lecture 1 Digital Session1 03:18:36
Lecture 2 Digital Session2 03:11:05
Lecture 3 Digital Session3 02:55:05
Lecture 4 Digital Session4 03:07:10
Lecture 5 Digital Session5 02:55:39
Lecture 6 Digital Session6 02:42:33
Lecture 7 Digital Session7 03:35:13
Lecture 8 Digital Session8 01:53:34
Lecture 1 Linux Session1 01:10:00
Lecture 2 Linux Session2 01:51:39
Lecture 3 Linux Session3 02:22:40
Lecture 4 Linux Session4 02:11:10
Lecture 5 Linux Session5 01:33:52
Lecture 6 Linux Session6 01:34:18
Lecture 1 PERL Session1 02:26:37
Lecture 2 PERL Session2 02:37:48
Lecture 3 PERL Session3 02:51:34
Lecture 4 PERL Session4 02:51:00
Lecture 5 PERL Session5 02:10:00
Lecture 6 PERL Session6 03:18:50
Lecture 1 TCL Session1 02:42:02
Lecture 2 TCL Session2 01:22:32
Lecture 3 TCL Session3 01:53:50
Lecture 4 TCL Session4 02:06:00
Lecture 5 TCL Session5 43:53:00
Lecture 6 TCL Session6 00:31:00
DFT Lecture 1 Introduction to DFT and Scan overview.(where dft fits in ASIC Flow, scan flow, scan styles(top-down, bottom-up), scan drc and scanability rule checks, test logic insertion. 03:10:23
DFT Lecture 2 Scan insertion - controllability, observability issues and violation during scan(internal clocks, tri-state buffers, feedback loops, latches, clock gaters etc) 03:14:00
DFT Lecture 3 Scan Insertion: Trainer1 03:08:04
DFT Lecture 4 Scan Insertion - clock domain and edge mixing, scan chain re-ordering, defining scan chain length and number of scan chains and different test cases. 03:56:24
DFT Lecture 5 . Introduction to compression : Need for compression, compression ratio, how to achieve test time and test data volume reduction using compression, impact of compression in the design, negative impacts of higher compression ratio, Tessent EDT architecture. 03:08:22
DFT Lecture 6 Compression continuation and synthesis-EDT architecture, internal - external flows, edt operation, bypass logic, x - masking, pipeline architecture, how to determine compression ratio for better compression (how to determine number of internal scan chain and external scan channel. 03:01:57
DFT Lecture 7 ATPG Introduction (Pattern generation introduction, Tessent fast scan, fault models, fault categories and fault classes, test types (stuck at, transition, IDDQ), test coverage and coverage analysis. 3:08:26
DFT Lecture 8 Scan, EDT and Synthesis Lab sessions 01:01:20
DFT Lecture 9 EDT and Synthesis Lab sessions 01:04:58
DFT Lecture 10 EDT revision, lab sessions and ATPG 02:53:10
DFT Lecture 11 ATPG: Fault models, fault categories, fault hierarchy, test type, inputs and outputs of ATPG necessary and files required to perform ATPG, test coverage debugging low test coverage using coverage analysis. 03:21:06
DFT Lecture 12 ATPG : multi cycle path, false path, timing implications, DRC's in ATPG, Scan chain tracing, fault classes 03:18:28
DFT Lecture 13 ATPG : Test types stuck at, transition, iddq and ATPG lab sessions and pattern generation, pattern types, pattern styles, writing faults lists. 02:18:40
DFT Lecture 14 ATPG 01:54:28
DFT Lecture 15 Compression (EDT and Synthesis) revision 02:44:25
DFT Lecture 16 Compression revision and EDT,ATPG labs 02:50:57
DFT Lecture 17 ATPG labs 02:36:59
DFT Lecture 18 Pattern simulations : pattern types - parallel and serial patterns, pattern formats (stil, wgl, verilog, input and or output files in pattern simulation) timing simulation and no timing simulation. 02:43:36
DFT Lecture 19 Pattern Simulations: (timing, setup, hold,) simulation script file explanation 01:41:54
DFT Lecture 20 Pattern Simulation using hands on : Dumping and loading waveforms in questa sim. Debugging simulation mismatches, causes of simulation mismatches, timing implications. 03:15:56
DFT Lecture 21 Simulation mismatches and mentor tessent OCC: on-chip clocking introduction, how to generate atspeed clocks,slow capture and fast capture, Tessent OCC architecture. 02:55:21
DFT Lecture 22 Boundary scan and IEEE 1149.1 JTAG: Jtag Tap machine, mandatory and optional instructions, IR registers and DR registers, bypass,boundary scan and extest modes. 3:02:30
DFT Lecture 23 JTAG and Introduction to MBIST : Tessent Mbist architecture,Mbist flow, memory models, memory faults, algorithms, Mbist hardware insertion. 2:59:30
DFT Lecture 24 Mbist : IEEE 1687 IJTAG introduction, IJTAG architecture, Mbist insertion - memory test, dft specification 2:52:30
DFT Lecture 25 MBIST : pattern specifications and icl extraction and pattern simulation. 3:01:00
DFT Lecture 26 TSDB Flow level 3 projects. Hierarchical DFT. 3:56:31
DFT Lecture 27 Mbist insertion, synthesis and simulation labs 3:03:30
DFT Lecture 28 TSDB Level 3 project labs 3:26:30
DFT Lecture 29 TSDB Level 3 project labs 3:12:30
DFT Lecture 30 DFT Session30 : Trainer1 3:34:30
DFT Lecture 31 DFT Session31 : Trainer1 3:04:20
DFT Lecture 32 DFT Session32 : Trainer1 2:53:30
DFT Lab Session 1 Scan labs 02:23:57
DFT Lab Session 2 Scan labs 02:28:08
DFT Lab Session 3 Scan labs 03:04:17
DFT Lab Session 4 Scan labs 03:38:23
DFT Lab Session 5 Simulation labs 03:34:22
DFT Lab Session 6 Simulation labs 03:33:57
DFT Lab Session 7 Simulation labs 2:34:26
DFT Lab Session 8 ATPG labs 02:50:20
DFT Lab Session 9 ATPG labs 02:45:58
DFT Lab Session 10 ATPG labs 02:44:10
DFT Lab Session 11 ATPG labs 02:38:06
DFT Lab Session 12 MBIST labs 04:07:28
DFT Lab Session 13 MBIST labs 03:48:40
DFT Lab Session 14 MBIST labs 03:46:28
DFT Lab Session 15 JTAG labs 02:44:25
DFT Lab Session 16 JTAG labs 02:16:57
DFT Lab Session 17 Level 2 project labs 03:42:59
DFT Lab Session 18 Level 2 project labs 03:34:36

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