Digital Design Training

About Course

Course Content:

Numbering system
Karnaugh maps
Timing diagrams
Various types of FF’s, Latch’s
Various Counters (with practical applications)
Data transfer synchronisation between components
Race condition
Meta stability
Multiplexer, Using MUX to create various gates, FF
Decoder, encoder, priority decoder
Parity generation
Half adder, full adder
Truth table for HA, FA, Mux, counters
Buffer, inverter
PLL, VCO, clock generation
Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies
Clock domain crossing
Power management in SOC
State machines
Predict design output
Gate level simulations
Debugging incorrect designs
Clock distribution
Active low and active high
Designing circuits for various requirements
CRC calculation logic
Pattern detector FSM
Interview focused questions
Give the circuit to extend the falling edge of the input by 2 clock pulses?
What are different ways multiply & Divide?
Target Audience:
BTech & MTech freshers looking for career opportunities in VLSI and Embedded System domains
Experienced engineers looking to enhance Digital Design advanced concepts
How this course helps?
Majority of VLSI, Embedded System fresher interviews focus on digital design concepts
All the VLSI Designs are driven by Digital and analog design concepts.  Good fundamentals helps with quick design understanding.
What if few sessions missed?
Course is organised once every 3 months. Student can repeat with no additional fee


Numbering system
Signed number
Unsinged number
1’s complement
2’s complement
Karnaugh maps
Truth table
Excitation table
Timing diagrams
Address bus
Data bus
Control signals
Handshake signals
Setup time
Hold time
FF using NOR
FF using J-K latch
FF using latch
How to calculate setup time, hold time
SR FF to JK FF conversion
DFF to TFF conversion
Difference between latch & Flipflop
Various types of FF’s, Latch’s
Counters (with practical applications)
Gray counter
Ring counter
Johnson counter
In a 3 bit Johnson counter, 2 states are unused, what are they
Modulo-n counter
Ripple counter
Synchronous FIFO
Asynchronous FIFO
Practical applications of FIFO
Difference between RAM & FIFO
What is FIFO? How to Calculate the Depth of FIFO?
Data transfer synchronization between components
Race condition
Show a design example with race condition
How to fix race condition
What is race around condition, how to fix it?
Meta stability
Use MUX to create AND, OR, NAND, NOR, XOR, XNOR
Use MUX to create FF, Latch
XOR to buffer
XOR to Inverter conversion
NAND to inverter
Design 4 input NAND gate using 2 input NAND gates
Design all gates using 2:1 MUX
input NAND gate using min no of 2 input NAND Gates
input NOR gate using min no of 2 input NOR Gates
input XNOR gate using min no of 2 input XNOR Gates
How to implement a Master Slave flip flop using a 2 to 1 Mux?
Design D Latch using 2:1 mux
Design D Latch from SR Latch
Decoder, encoder, priority decoder
Parity generation
Practical uses of parity generation
Half adder, full adder
FA using HA
Truth table for HA, FA, Mux, counters
Buffer, inverter
Practical uses
PLL, VCO, clock generation
PLL LMN parameters
Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies
Clock domain crossing
What are the different ways synchronize between two clock domains?
Synchronizers : 2 stage, 3 stage
Practical uses, how reset distribution works
Synchronous reset, Asynchronous reset
Power management in SOC
State machines
Gray code encoding
One-hot encoding
Binary encoding
Moore state machine
Mealy state machine
Difference between Moore and Mealy state machines
Using FF
How they function
How they are modeled
Given RTL code, draw the synthesis diagram
Predict design output
Given a design with various gates and FF, draw the timing diagram
Predict the output
Gate level simulation
What is x-prop
Different causes of x-prop
SDF format
Different types of delays in digital circuits
Propagation delay
Rise delay, fall delay
Transmission delay
How to fix setup time violation
How to fix hold time violation
What is multi cycle path
What is false path, impact on circuit operation
Why multi stage synchronizers are masked for x-prop checks
Clock distribution
Draw a logic to distribute clock for minimal clock latencies in various blocks of SOC
How to minimize clock jitter
How to reduce clock latency
How clock gating works
How to achieve 180 degrees phase shift
Clock skew? How to reduce clock skew?
What is glitch? What causes it (explain with waveform)? How to overcome it?
Active low and active high
Why interrupts are active low
How do we achieve multiply and division using register shift
How to achieve multiple by 3 using shift?
Write gate logic to compare 2 8-bit signals
Difference between full substractor and half substractor
Implement full substractor from full adder
Digital design interview questions
The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate the direction of rotation.
You have two counters counting upto 16, built from negedge DFF , First circuit is synchronous and second is “ripple” (cascading), Which circuit has a less propagation delay? Why?
Design a circuit for finding the 9’s complement of a BCD number using 4-bit binary adder and some external logic gates?
Design a circuit that calculates square of a number
CRC calculation logic
Logic diagram
Pattern detector FSM
Give the circuit to extend the falling edge of the input by 2 clock pulses?
Circuit design for various requirements

Course videos

Lecture 1 Digital Session1 03:47:36
Lecture 2 Digital Session2 03:37:05
Lecture 3 Digital Session3 03:48:05
Lecture 4 Digital Session4 03:45:10
Lecture 5 Digital Session5 03:39:39
Lecture 6 Digital Session6 03:53:33
Lecture 7 Digital Session7 03:25:13
Lecture 8 Digital Session8 03:19:34
Lecture 9 Digital Session9 03:57:34
Lecture 10 Digital Session10 03:50:34
Lecture 11 Digital Session11 03:57:34
Lecture 12 Digital Session12 04:02:34
Lecture 13 Digital Session13 03:57:34
Lecture 14 Digital Session14 01:49:34
Lecture 15 Digital Session15 01:53:34

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