DMA Controller Functional Verification

About Course

DMA controller is an important aspect of every SOC, which is used for peripheral to peripheral, peripheral to memory and memory to memory data transfers with minimal intervention from Processor. Current DMA controller design has 2 cores with 8 channels per core.

DMA controller functional verification using SV & UVM, covers all the aspects of verification starting from reading the specifications, feature list down, testbench development, testbench component coding, register model development, testcase coding and regression setup, debug for coverage analysis. Course gives indepth overview of sequence development, debugging of complete testcases, etc. Course also introduces to functional and code coverage analysis.


Feature list down
Testplan development
Functional coverage point list down
Register list down
Testbench architecture definition
TB component coding
Register model coding
TB component integration
Testcase development
Register access tests: reset and wr-rd testcases
Functional testcase coding
Test case debug
Regression setup using PERL script
Regression and coverage report generation
Functional and code coverage analysis
Updating tests for coverage closure
Adding new tests for coverage closure

Course videos

Lecture 1 Course overview, Significance of DMA in SOC , Understanding the Design specification for any project, DMA Controller overview, DMA controller architecture, DMA controller features, DMA CPU functions(copying data, peripheral control,) Core optional features, DMA controller main features, Port description, Types of Operations, DMA Operation modes, DMA command. 3:00:13
Lecture 2 Questions on Channel, AXI Bus synchronizer, Peripheral control, DMA controller feature implementation, DMA controller registers, DMA controller modes, DMA operation modes(Core1, Core2), DMA commands, Configuration flows(General configuration, configure and start a channel, stop a channel, Pause and resume a channel, Restart a channel, Interrupt handling, Implementing the test cases. 3:17:19
Lecture 3 DMA controller channels, Different modes of DMA Controller operation, Steps for executing DMA controller, Functional verification steps, DMA Controller features, Functional coverage point listing down, Sanity test cases, Test bench Architecture, TB component coding(top module, interface declaration, generating clk&rst, program block, env block, All sub envs). 4:18:16
Lecture 4 Resolving the debugging issue of test_reg_wr_rd(hanging), Implementing logic to check the register mismatches, Need of Register masks& Register model, Write_reg, Read_reg, Reserved fields in Register, Why channel_reg_maskA is 248? (static bit[31:0] channel_reg_maskA[248], Why shared_reg_maskA is [63:0]?(static bit [31:0] shared_reg_masksA[63:0];) 3:33:52
Lecture 5 Sanity test case coding, Channel base address, Register indexes, Generating a new register block with updated list of registers, Integrated that into the Environment, test_reg_wr_rd, test_reg_reset(Tracing the failures through RTL files), Developing a functional test for DMA transfer from 32'h0001_0000 to 32'h0002_0000. 3:37:52
Lecture 6 Basic DMA transfer test Analysis, Reference model, DUT Configuration, Adding few more tests, CMD list based transfer, Functional Coverage, Generating Coverage Report, Adding 5 test cases, Analysing code coverage, Trying to improve the coverage, Updating for handling CMD list based transfers, Creating regression script, Running regression test, 3:35:25
Lecture 7 Adding new test cases, Implementing Assertions, Implementing Functional coverage covergroups, Improving the coverage, IDLE, READY_OUT, Analysing the RTL Signals, Peripheral transfers, RX Peripheral, Registers Configuration(RD_BURST_MAX_SIZE, RD_PERIPH_NUM, RD_TOKENS, RD_PERIPH_DELAY). 3:48:05
Lecture 8 Implementing Functional Coverage, Implementing Assertions, Adding few test cases(peripheral transfers, tests failing with some errors), Improving functional coverage and code coverage. 4:39:25
Lecture 9 Developing more test cases for coverage improvement, Peripheral transfer configuration(RD_BURST_MAX_SIZE, RD_PERIPH_NUM, RD_TOKENS, RD_PERIPH_DELAY), Is BLOCK MODE compulsory for Peripheral transfer?, Coverage Report Analysis. 3:19:25

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