FPGA Design and Verification Training

About Course

FPGA course is a 6 months course provides in depth exposure to complete FPGA system design flow starting from RTL coding, prototyping and validation.


FPGA Architecture
FPGA internals and I/0
FPGA timing closure
FPGA implementation by RTL mode as well as IP Mode
FPGA debugging
Software development kit environment
Booting FPGA in petalinux/ubuntu

Curriculum

+
Specification
RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
DFT
Custom layout
Post silicon validation
+
Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Memories
Refer to Advanced digital design training page for detailed course contents
www.vlsiguru.com/digital-design-complete
+
Shells
File and directory management
User administration
Environment variables
Commonly used commands
Shell scripting basics
SEd and AWK
Revision management
Makefiles
+
SOC Architecture overview
SOC design concepts
SOC verification concepts
SOC Components
SOC use cases
SOC Testbench architecture
SOC Test Case coding
SOC verification differences with module verification
+
Verilog language constructs
Verilog design coding examples covering more than 20 standard designs
www.vlsiguru.com/verilog-training/
+
PAL, CPLD and FPGA basics
FPGA Design Flow
+
Internals of FPGA and CPLD
Logic implementation
FPGA Architectures of various FPGA vendors
Anti-fuse and SRAMS
Logic elements and Look-up Tables
Dedicated multipliers
Distributed RAM
Shift registers
MMCM
Kintex
Zynq
Virtex Architectures
+
Introduction and usage of IP coresĀ·
+
Modelsim/Icarus Verilog simulation
Design Synthesis
+
Design constraining and pin locking
Timing analysis
slack calculation
Data loss due to large skew
Maximum skew calculations with examples
Period constraints
Area and Power Constraints
Static Timing Analysis
FPGA programming
Translate
Map
Floor plan
Place and Route
Post map and Post P&R simulation
XDC constraints
Reading and analysing reports-post synthesis
Post map simulation
Post PĀ·&R simulation
Configuring FPGAs
FSM Extraction
+
Timing Simulation using Modelsim/Icarusverilog
Programming using JTAG
+
Debugging techniques
Debugging using chip scope and Logic analyzers
Protocols on FPGA
High Speed SERDES
Identification of the issues/resolving
+
FPGA SDK environment
FPGA Device selection
+
PERL Interpreter
Variables
File management
Subroutines
Regular expressions
Object oriented PERL
PERL modules
+
Facing interviews effectively
industry work culture
Group discussions
+
100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting

Course videos

+
Lecture 1 VLSI Design flow Session1 02:52:37
Lecture 2 VLSI Design flow Session2 02:01:39
Lecture 3 Digital Session1 03:18:36
Lecture 4 Digital Session2 03:11:05
Lecture 5 Digital Session3 02:55:05
Lecture 6 Digital Session4 03:07:10
Lecture 7 Digital Session5 02:55:39
Lecture 8 Digital Session6 02:42:33
Lecture 9 Digital Session7 03:35:13
Lecture 10 Digital Session8 01:53:34
Lecture 11 Linux Session1 01:10:00
Lecture 12 Linux Session2 01:51:39
Lecture 13 Linux Session3 02:22:40
Lecture 14 Linux Session4 02:11:10
Lecture 15 Linux Session5 01:33:52
Lecture 16 Linux Session6 01:34:18
Lecture 17 PERL Session1 02:26:37
Lecture 18 PERL Session2 02:37:48
Lecture 19 PERL Session3 02:51:34
Lecture 20 PERL Session4 02:51:00
Lecture 21 PERL Session5 02:10:00
Lecture 22 PERL Session6 03:18:50
Lecture 23 Verilog Session1 03:00:13
Lecture 24 Verilog Session2 03:17:19
Lecture 25 Verilog session3 04:18:16
Lecture 26 Verilog Session4 03:32:52
Lecture 27 Verilog Session5 03:37:52
Lecture 28 Verilog Session6 03:35:25
Lecture 29 Verilog Session7 04:35:08
Lecture 30 Verilog Session8 04:39:25
Lecture 31 Verilog Session9 03:19:25
Lecture 32 Verilog Session10 04:02:39
Lecture 33 Verilog Session11 03:22:14
Lecture 34 Verilog Session12 02:46:52
Lecture 35 Verilog Session13 01:30:00
Lecture 36 Verilog Session14 00:25:30
Lecture 37 Verilog Session15 02:03:00
Lecture 38 Fpga Session1 3:00:13
Lecture 39 Fpga Session2 3:17:19
Lecture 40 Fpga Session3 4:18:16
Lecture 41 Fpga Session4 3:33:52
Lecture 42 Fpga Session5 3:37:52
Lecture 43 Fpga Session6 3:35:25
Lecture 44 Fpga Session7 4:35:08
Lecture 45 Fpga Session8 4:39:25
Lecture 46 Fpga Session9 3:19:25
Lecture 47 Fpga Session10 4:02:39
Lecture 48 Fpga Session11 3:22:14
Lecture 49 Fpga Session12 2:46:53
Lecture 50 Fpga Session13 1:27:46
Lecture 51 Fpga Session14 0:25:41
Lecture 52 Fpga Session15 0:25:41
Lecture 53 Fpga Session16 0:25:41
Lecture 54 Fpga Session17 0:25:41
Lecture 55 Fpga Session18 0:25:41
Lecture 56 Fpga Session19 0:25:41
Lecture 57 Fpga Session20 0:25:41
Lecture 58 Fpga Session21 0:25:41
Lecture 59 Fpga Session22 0:25:41
Lecture 60 Fpga Session23 0:25:41
Lecture 61 Fpga Session24 0:25:41
Lecture 62 Fpga Session25 0:25:41
Lecture 63 Fpga Session26 0:25:41
Lecture 64 SOC Design and verification 03:09:23
Lecture 65 Revision Management 02:00:00


Benefits of eLearning:

  • - Access to the Instructor - Ask questions to the Instructor who taught the course
  • - Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • - Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

continue to register

Have an account ? Login Fast

Login to Continue

If you face any Issue Contact Administrator.