PCIe Data link Layer UVC Development Training

About Course

PCIe Data link layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and DLL-TL interface. These UVC are integrated with DLL RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding. Sessions also focused on developing the sequences for AXI, TL-DLL and DLL-PL interfaces, using these sequences to create the testcases. Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.



Curriculum

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Introduction
Protocol overview
Features
Scenarios
Verification plan
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Data link layer RTL coding
DLL Testbench architecture, testplan development
UVC architecture and components
UVC component coding
AXI UVC, DLL-TL and DLL-PL UVC
Testbench component integration
UVC sequence coding for AXI and DLL interface
Testcase coding
Testcase run and waveform analysis
Testbench integration
Simulations and waveform analysis
Functional coverage analysis

Course videos

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Lecture 1 PCIe DLL overview 03:00:15
Lecture 2 PCIe DLL features, scenario, testplan 02:47:01
Lecture 3 Testbench architecutre, UVC development 02:00:16
Lecture 4 PCIe DLL RTL coding 02:00:16
Lecture 5 PCIe DLL RTL coding 03:00:15
Lecture 6 AXI UVC coding 02:47:01
Lecture 7 DLL-TL and DLL-PL UVC coding 02:00:16
Lecture 8 UVC integration in to testbench 02:00:16
Lecture 9 Sequence coding and testcase coding 03:00:15
Lecture 10 Testcase debug and waveform analysis 02:47:01
Lecture 11 Testcase coding 02:00:16
Lecture 12 Regression setup and coverage analysis 02:00:16


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