RTL Design and Integration Training

About Course

RTL Design and Integration Course is of 5 months duration focused on enabling participant with RTL integration job role. Training focus will be on RTL coding using Verilog & VHDL, manual integration, developing the glue logic during integration, tool based integration, linting, CDC, UPF, Synthesis and STA.


VLSI Front end domain(Pre-synthesis flow) jobs can be classified in to multiple categories as RTL coding, RTL integration, and Functional verification. VLSI design flow is completely driven by design IP reuse, hence majority of jobs in front end design will be based on RTL integration, which involves integrating multiple IP's in to SOC as per architecture requirements. RTL integration engineer requires good exposure to RTL coding, Design constraints, Digital design concepts, good coding guidelines and exposure to Synthesis and STA concepts.


Majority of the training institutes are focused on Functional verification Course only(with no training on RTL design & integration), which means there are very few trained resources in RTL Design and integration domain, which makes it easy to find a job in front end domain as a RTL integration engineer. Statistics is for every 5 verification engineers, at least one RTL integration engineer will be required.  1000+ students getting trained in Functional verification(across institutes in Bangalore, Hyderabad, Noida, etc), compare this with 10's of students getting trained in RTL integration. Hence RTL Integration course will give you edge compared to functional verification course.
... Like any other job role in VLSI design flow, RTL integration is also a tool intensive job. RTL Integration course will provide the student with expertise on Synopsys Spyglass(Lint and CDC), Design compiler for Synthesis and Primetime for STA. Tools helps with quick turn around in time critical projects, where integration engineer is expected to release the design tag in short timelines. With growing design complexity and reducing timelines, it requires efficient techniques for RTL connectivity and developing the logic for various blocks integration. LINTING is a static analysis of the RTL code based on some set of rules and guidelines. When these rules or guidelines are broken, LINT tool flags errors or warnings, which need to be reviewed, fixed or waived by designer. This course discusses good amount of LINT rules and guidelines, which will enable audience to gain good design practices and perform LINTING if needed.
Course will also focus on Splyglass based CDC(Clock domain crossover) for the synchronisation of various signals moving across one clock domain to another. Course will focus on in-depth analysis of Lint and CDC checks with hands on integration project.
Similar to how we have multiple clocks in a System-On-Chip design we do have multiple power domains being used in modern SOCs for different reasons. Unified Power Format is IEEE standard developed by Accellera. This is used to ease the job of specifying, simulating and verifying the design with multiple power states and power islands. UPF is designed to specify power intent of a design at high level. UPF scripts mention the details of which power rails need to be connected to which IP, whether the register values need to be retained during power off, whether we need an isolation of design in case of power down and manages voltage levels shift as signals cross from one power domain to the other. In this course we discuss the need for multiple power domains, basics of UPF and some examples.
In today’s era, complex SoC chips are being realised using complex VLSI(EDA) tools, of which RTL2GDSII flow is being used extensively during any SoC manufacturing. This has enabled the realisation of very complex digital designs, which starts with design specification and modelling of design using HDL language. This high-level description of the design is mapped to its corresponding hardware using automation, known as “Synthesis,” without which it’s near to impossible to design very complex digital circuits.

Curriculum

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Specification
RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
Custom layout
Post silicon validation
Specification
RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
DFT
Custom layout
Post silicon validation
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Revision Management
IBM Clearcase
Perforce
GIT
Project Management
Detailed overview of project phases
Significance of RTL integration in VLSI Design Flow
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Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Memories
Setup time, Hold time, timing closure, fixing setup time and hold time violations
STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
www.vlsiguru.com/digital-design-complete
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Shells
File and directory management
User administration
Environment variables
Commonly used commands
Shell scripting basics
SEd and AWK
Revision management
Makefiles
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Introduce TCL
Why TCL?
TCL Script Processing
Understand TCL uses and strengths
Writing simple TCL scripts
TCL for VLSI scripting
TCL : Main Features
TCL in EDA
TCL shell (tclsh)
Working with TCL scripts (UNIX)
TCL Interpreter in SoC Design Tools
TCL Scripting for SoC Design
TCL Commands
Variables
Substitution and Command Evaluation
Operators
Mathematical Functions
Procedures
Control flow : if, if-else, switch, for, foreach, while, break and continue
String, string operations
List, List manipulation
Arrays, array methods
Working with files
Command line arguments
Regular expressions
Complete TCL Scripts
TCL Packages
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Detailed overview of all Verilog-2001 constructs
Multiple hands on projects
Pattern detector
Synchronous and Asynchronous FIFO
Interrupt controller
SPI Controller
Watchdog timer
PISO and SIPO
Vending machine
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Overview of RTL Integration
Manual RTL integration
Need for Tool based Integration
coreTools Basics
Usage model for IP packaging
Usage model for IP integration
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• Purpose of LINTING
• SpyGlass Lint Tool Flow
• Rules in SpyGlass Lint
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CDC Basics
CDC Analysis
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Introduction to Low Power
Power Intent and UPF
Special low power cells and requirements
Introduction to SpyGlass LP Static Check
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Introduction to Synthesis
Data Setup for DC
Accessing Design and Library Objects
Constraints: Reg-to-Reg and I/O Timing
Constraints: Input Transition and Output Loading
Constraints: Multiple Clocks and Exceptions
Constraints: Complex Design Considerations
Post-Synthesis Output Data
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Basic concepts of Formal verification and LEC
Input generation for LEC
Hands on project
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2 Hands on projects based on complete RTL integration flow, CDC, Lint, Synthesis and STA

Course videos

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Lecture 1 VLSI Design flow Session1 02:52:37
Lecture 2 VLSI Design flow Session2 02:01:39
Lecture 3 Digital Session1 03:18:36
Lecture 4 Digital Session2 03:11:05
Lecture 5 Digital Session3 02:55:05
Lecture 6 Digital Session4 03:07:10
Lecture 7 Digital Session5 02:55:39
Lecture 8 Digital Session6 02:42:33
Lecture 9 Digital Session7 03:35:13
Lecture 10 Digital Session8 01:53:34
Lecture 11 Linux Session1 01:10:00
Lecture 12 Linux Session2 01:51:39
Lecture 13 Linux Session3 02:22:40
Lecture 14 Linux Session4 02:11:10
Lecture 15 Linux Session5 01:33:52
Lecture 16 Linux Session6 01:34:18
Lecture 17 PERL Session1 02:26:37
Lecture 18 PERL Session2 02:37:48
Lecture 19 PERL Session3 02:51:34
Lecture 20 PERL Session4 02:51:00
Lecture 21 PERL Session5 02:10:00
Lecture 22 PERL Session6 03:18:50
Lecture 23 Verilog Session1 03:00:13
Lecture 24 Verilog Session2 03:17:19
Lecture 25 Verilog session3 04:18:16
Lecture 26 Verilog Session4 03:32:52
Lecture 27 Verilog Session5 03:37:52
Lecture 28 Verilog Session6 03:35:25
Lecture 29 Verilog Session7 04:35:08
Lecture 30 Verilog Session8 04:39:25
Lecture 31 Verilog Session9 03:19:25
Lecture 32 Verilog Session10 04:02:39
Lecture 33 Verilog Session11 03:22:14
Lecture 34 Verilog Session12 02:46:52
Lecture 35 Verilog Session13 01:30:00
Lecture 36 Verilog Session14 00:25:30
Lecture 37 Verilog Session15 02:03:00
Lecture 38 RTL Session1 03:38:17
Lecture 39 RTL Session2 02:03:18
Lecture 40 RTL Session3 01:18:00
Lecture 41 RTL Session4 02:53:01
Lecture 42 RTL Session5 03:21:33
Lecture 43 RTL Session6 02:39:25
Lecture 44 RTL Session7 02:20:47
Lecture 45 RTL Session8 01:37:07
Lecture 46 RTL Session9 03:02:18
Lecture 47 RTL Session10 02:35:40
Lecture 48 RTL Session11 01:47:20
Lecture 49 RTL Session12 01:58:06
Lecture 50 RTL Session13 01:57:07
Lecture 51 RTL Session14 03:21:33
Lecture 52 RTL Session15 01:14:35


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