SOC Design and Verification

About Course

SOC design & verification flow overview
SOC Design concepts
Processor boot concepts
SOC Verification : Important aspects
Testbench
Setting up SOC TB environment
SOC Subsystem overview (Processor, High speed, Low speed, Modem, Multimedia subsystem)
Testplan
Testcase Flow
Testcase Coding (C & SV)
Running testcases & regression
SOC Test debug ...
Typical testcase issues
Verification closure
Performance requirements
Gate level simulations
Power Aware Simulations
PAGLS
EVCD generation
Vector runs on VT setup
Generating binaries for running on tester
ECO
RMA
UVC in Testbench setup & sequence usage in SV testcase
SOC FLOW:
SoC Architecture
Design Integration
Spy glass,
Functional Verification
Formal Verification (Connectivity Checks)
PA RTL simulations
GLS
PA GLS simulations (UPF)
Vector evcd generation
VT simulations on testers
Post silicon validation (VI)
Design:
SoC Architecture
SoC Interconnects & NOCs
NoC Overview – Types of NOCs, purpose and diagram
SoC Digital & Analog Components
SoC Address Mapping
SoC Interrupt Mapping
SoC Frequency Plan
SoC Performance requirements
Features
DPLL
SoC Memories: Msg ram, Iram, DDR, Flash
SoC Subsystems
Low Power Verification
UPF
Important aspects:
SoC Architecture, understanding transaction matrix
Processor boot, SCF file,
interconnects
Memory preloading
DDR initialization
PLL locking(LMN values)
TIC interface
Clock domains
Different clock mode
XO mode, at-speed mode
Interrupt handler
Processor interfaces: interfaces meant for fetching instruction, data code
I/O’s of SOC: Dedicated IO’s, and GPIOs
GPIO purpose : Pad muxing
CDC
Cycle slips
MMU, Physical address, virtual address
ARM instruction set basics
Types of verification : how they are different
Processor architectures
ARM, ARC, DSP
Cortex A series, M series
Impact on design architecture
Basics of ARM processors
Types of processors – Cortex-M series, A series.
ARM C, ASM compiler, linker.
Caches (L1 and L2).
Generic Interrupt controller.
Exceptions, Events – Types of Exceptions (Edge, Level), Source of Exceptions, How to handle.
Debug system – Basics of ARM debug sub system.
Scatter files.
How to set reset location to start booting.
Loading C code into memories – Front door, back door.
ARM Instruction example
SOC Testbench Setup
SoC environment structure
SoC TB Architecture
Integrating UVC in to SoC TB
SoC Processor-TB interaction
Testplan:
register wr-rd, reset tests
Interrupt tests
targeting different frequency plans
Feature(use-case) tests
power aware tests
Fuse tests
End to end data transfer tests
Booting from different testcases
Address decoding access tests
Connectivity tests
Testcase Flow:
TIC mode
Functional mode
Device Initialization
DDR initialization
Enabling DDR access to different processors
Processor boot sequence
Processor boot from different memories
C test Main function
Power uncollapse
Functional test
Coding testcases:
Listing down test requirements, pass criteria
Power domains to be up
clock domains to be up, required frequencies
Understanding required flow to implement testcase
knowing library functions to implement above flow
understanding handshake between Native & SV code
Setting up environment:
Design baseline
all design sub component latest baselines
verif baseline
all verif sub component latest baselines
Updating env for custom baseline
Running testcases & regression:
Command line
sim_gui mode
Command line options
using force files, timing corners, frequency plans
Debugging tests:
tarmac log
List file
mpf file
log
Wave dump debug
Message based debug
Warnings, errors
Typical testcase issues:
Processor not booting
register looping
Not working at current frequency plan
pll not locked
Memory not preloaded
clocks not running
Access is not enabled to register or memory space
Simulation not proceeding in time
Simulation is proceeding in time but not completing (looping)
Interrupt not serviced
interrupt not generated
Signal not sampled
sub module functional issues
Denali errors
Memory loading ‘x’ debug
tied signals, unconnected ports
Understanding chip stages:
RTL code freeze
Base tapeout
Metal tapeout
ECO update
CS (customer shipment)
RMA
Verification closure:
Regression 100% pass
100% toggle coverage
reviews high level & low level
Performance requirements
Power reqs met
Performance requirements?
Gate level simulations:
Significance
choosing tests for GLS
EVCD generation:
Format?
Why?
choosing tests for GLS
Vector runs on VT setup
production vectors
characterization vectors
Generating binaries for running on tester
Vector debug
ECO:
What stage ECO is issued
RMA:
Significance?
Misc:
SoC Architecture:
SoC Interconnects
SoC Digital & Analog Components
SoC Address Mapping
SoC Interrupt Mapping
SoC Frequency Plan
SoC Performance requirements
Features
PLL
SoC Memories: Msg ram, Iram, DDR, Flash
Processor booting from different memories
UVC in Testbench setup & sequence usage in SV testcase

Curriculum

+
SOC design & verification flow overview
SOC Design concepts
Processor boot concepts
SOC Verification : Important aspects
Testbench
Setting up SOC TB environment
SOC Subsystem overview (Processor, High speed, Low speed, Modem, Multimedia subsystem)
Testplan
Testcase Flow
Testcase Coding (C & SV)
Running testcases & regression
SOC Test debug
Typical testcase issues
Verification closure
Performance requirements
Gate level simulations
Power Aware Simulations
PAGLS
EVCD generation
Vector runs on VT setup
Generating binaries for running on tester
ECO
RMA
UVC in Testbench setup & sequence usage in SV testcase
+
SoC Architecture
Design Integration
Spy glass,
Functional Verification
Formal Verification (Connectivity Checks)
PA RTL simulations
GLS
PA GLS simulations (UPF)
Vector evcd generation
VT simulations on testers
Post silicon validation (VI)
+
SoC Architecture
SoC Interconnects & NOCs
NoC Overview – Types of NOCs, purpose and diagram
SoC Digital & Analog Components
SoC Address Mapping
SoC Interrupt Mapping
SoC Frequency Plan
SoC Performance requirements
Features
DPLL
SoC Memories: Msg ram, Iram, DDR, Flash
SoC Subsystems
Low Power Verification
SoC Architecture
SoC Interconnects & NOCs
NoC Overview – Types of NOCs, purpose and diagram
SoC Digital & Analog Components
SoC Address Mapping
SoC Interrupt Mapping
SoC Frequency Plan
SoC Performance requirements
Features
DPLL
SoC Memories: Msg ram, Iram, DDR, Flash
SoC Subsystems
Low Power Verification
UPF
+
SoC Architecture, understanding transaction matrix
Processor boot, SCF file,
interconnects
Memory preloading
DDR initialization
PLL locking(LMN values)
TIC interface
Clock domains
Different clock mode
XO mode, at-speed mode
Interrupt handler
Processor interfaces: interfaces meant for fetching instruction, data code
I/O’s of SOC: Dedicated IO’s, and GPIOs
GPIO purpose : Pad muxing
CDC
Cycle slips
MMU, Physical address, virtual address
ARM instruction set basics
Types of verification : how they are different
Processor architectures
ARM, ARC, DSP
Cortex A series, M series
Impact on design architecture
Basics of ARM processors
Types of processors
Cortex-M series, A series.
ARM C, ASM compiler, linker.
Caches (L1 and L2).
Generic Interrupt controller.
Exceptions, Events
Types of Exceptions (Edge, Level), Source of Exceptions, How to handle.
Debug system
Basics of ARM debug sub system.
Scatter files.
How to set reset location to start booting.
Loading C code into memorie
Front door, back door.
ARM Instruction example
+
SoC environment structure
SoC TB Architecture
Integrating UVC in to SoC TB
SoC Processor-TB interaction
+
register wr-rd, reset tests
Interrupt tests
targeting different frequency plans
Feature(use-case) tests
power aware tests
Fuse tests
End to end data transfer tests
Booting from different testcases
Address decoding access tests
Connectivity tests
+
TIC mode
Functional mode
Device Initialization
DDR initialization
Enabling DDR access to different processors
Processor boot sequence
Processor boot from different memories
C test Main function
Power uncollapse
Functional test
+
Listing down test requirements, pass criteria
Power domains to be up
clock domains to be up, required frequencies
Understanding required flow to implement testcase
knowing library functions to implement above flow
understanding handshake between Native & SV code
+
Design baseline
all design sub component latest baselines
verif baseline
all verif sub component latest baselines
Updating env for custom baseline
+
Command line
sim_gui mode
Command line options
using force files, timing corners, frequency plans
+
tarmac log
List file
mpf file
log
Wave dump debug
Message based debug
Warnings, errors
+
Processor not booting
register looping
Not working at current frequency plan
pll not locked
Memory not preloaded
clocks not running
Access is not enabled to register or memory space
Simulation not proceeding in time
Simulation is proceeding in time but not completing (looping)
Interrupt not serviced
interrupt not generated
Signal not sampled
sub module functional issues
Denali errors
Memory loading ‘x’ debug
tied signals, unconnected ports
+
RTL code freeze
Base tapeout
Metal tapeout
ECO update
CS (customer shipment)
RMA
+
Regression 100% pass
100% toggle coverage
reviews high level & low level
Performance requirements
Regression 100% pass
100% toggle coverage
reviews high level & low level
Performance requirements
Power reqs met
Power reqs met
+
15.Gate level simulations:
Significance
choosing tests for GLS
16.EVCD generation:
Format?
Why?
choosing tests for GLS
17.Vector runs on VT setup
production vectors
characterization vectors
18.Generating binaries for running on tester
Vector debug
19.ECO:
What stage ECO is issued
20.RMA:
Significance?
+
PLL
SoC Architecture:
SoC Interconnects
SoC Digital & Analog Components
SoC Address Mapping
SoC Interrupt Mapping
SoC Frequency Plan
SoC Performance requirements
Features
SoC Memories: Msg ram, Iram, DDR, Flash
Processor booting from different memories
UVC in Testbench setup & sequence usage in SV testcase

Course videos

+
Lecture 1 SOC Session1 02:56:54
Lecture 2 SOC Session2 03:05:38
Lecture 3 SOC Session3 02:59:21
Lecture 4 SOC Session4 02:58:58
Lecture 5 SOC Session5 03:02:27
Lecture 6 SOC Session6 03:03:42
Lecture 7 SOC Session7 02:36:59
Lecture 8 SOC Session8 02:25:17
Lecture 9 SOC Session9 02:46:02
Lecture 10 SOC Session10 02:02:02
Lecture 11 SOC Session11 01:45:02
Lecture 12 SOC Session12 02:10:00


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