TCL for VLSI flow automation training

About Course

Application Oriented TCL for Synopsys Tools

TCL training is for VLSI professionals and students who work on Synopsys tools like ICC/ICC2 Compiler, DFT Compiler, Design Compiler , Primetime. Training will enhance your scripting skills which increase your productivity while using Synopsys tools. Real time Projects/Assignments will be given to audience as well as driven by audience requirements.Explanation and Execution of all concepts, commands and scripts will done in ICC shell to connect to audience requirements. VPN will be given to audience for practice and execution of projects/assignments. Tools Used for TCL Scripting : ICC2, Primetime, Design Compiler



... All the EDA tool flows from Synopsys, Cadence and Mentor Graphics use Tcl as the primary scripting interface for their flows. TCL as a single command language in all EDA tool flows ensures that a designer only needs to learn Tcl in order to work with all the flows.

TCL scripting is much sought after skill set for every VLSI engineer. Training will provide the detailed practical exposure on each aspect of project flow setup mostly focused on Physical Design, STA, and functional verification with multiple hands on examples.

Curriculum

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Overview
Env Setup
Special Variables
Data Types
Variables
Operators
Decisions
Loops
Arrays, Strings, Lists, Dictionary
History and Redoing of commands
String Pattern Matching commands
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Unit 1: File Operations
Lab 1: Scripts on file operations.
Unit 2 : Usage of redirect command
Lab 2 : Execution of redirect commands
Unit 3 : Control Flow, Math Functions
Lab 3 : Execution of Control Flow, Maths Functions.
Unit 4: Procedures
Lab 4 : Writing own Procedural commands.
Unit 5: Procedures with positional arguments
Lab 5: Writing own Procedures with positional arguments
Unit 6 : Procedures with non positional arguments (switch based procedures)
Lab 6 : Writing own Procedures with non positional arguments.
Unit 7: Object Classes and Design Objects
Lab 7 : Commands to handles design objects
Unit 8 : Collections
Lab 8 : Commands to handle Collections
Unit 9 : Design objects Collection and its attributes
Lab 9 : Scripts on collections and its attributes
Unit 10 : Linking design objects with another design objects.
Lab 10: Scripts on linking design objects with another design objects.
Unit 11 : Filtering applications on design objects.
Lab 11 : Scripts on filtering applications
Lab 12: Script to get gate count of full chip.
Lab 13: Script for macro placement.
Lab 14: Script for finding high fan out nets
Lab 15: Script on ECO fixing like inserting buffers on high fan out nets
Lab 16: Script on inserting antenna diodes to fix antenna violations.
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Script to write customize pin placement.
Script to write TCL file to execute some set of command from the collection (it can be a file or variable).
Script to find shorted (nets having shorts) nets.
Script to improve the routing of bad nets.
Script to insert buffer to all endpoints having hold violations.
Script to resolve overlapping even after legalize placement.
Script for handling logs from different Synopsys tools.
Script to report endpoints and start points slack of top 1000 failing paths
Script to get a list of the register sinks for a clock
Script to return all the instance pins that are in timing path.
Script to report slack and difference between clock arrival time at launch and capture clocks.
Script to report logics between reg to reg path. This script can be modified for different path groups.
Script to find the number of logic levels(combinational) in a timing path or group of timing paths.
Script to report worst slack for all clock group.
Dedicated projects based on audience requirements
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Assignments based on TCL flow automation for various aspects of VLSI backend flow.

Course videos

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Lecture 1 TCL Session1 56:38
Lecture 2 TCL Session2 02:05:38
Lecture 3 TCL Session3 02:03:33
Lecture 4 TCL Session4 01:51:19
Lecture 5 TCL Session5 01:47:51
Lecture 6 TCL Session6 01:50:45
Lecture 7 TCL Session7 02:02:09
Lecture 8 TCL Session8 02:57:35


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