Verilog for Design and Verification

About Course

Verilog for Design & Verification (VG-VERILOG) is a 46 hours of theory and 30 hours of labs course with detailed emphasis on Verilog for complex design implementation and verification. VT-VERILOG course is targeted for both design & verification engineers to gain expertise in Verilog for design & testbench development. This is must do course for every electronics and electrical graduate. Student may also opt for course on advanced digital design and basic analog design conceptsAdvanced Digital Design Training.

Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple design implementation examples and testbench setup for the same, and all these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VERILOG



...Verilog language constructs with detailed examples on each construct usage
Multiple Design Coding & Testbench development
Access to Questasim tool
Hands on labs & Hands on projects

Curriculum

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How Verilog differs from other programming languages?
Verilog language concepts
Registers, nets
Vectors, Array
Memories
Data types
Operators
Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
Procedural Blocks
Continuous assignments
Procedural Statements
Generate
State Machines
Gate Level Implementation
Hierarchical modeling
Verilog Programming Interface(& PLI)
Pipelining
FSM : Mealy and Moore
FSM State encoding styles
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Flipflop (Synchronous & Asynch Reset), Latch
Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
Shift register implementation
Half adder, full adder, multiplexer
Dual port memory write, read design & testbench
encoder, decoder, various gates
Primitive implementation using table, endtable
Pattern detector
Coin counter for tea vending machine
Traffic light controller(TLC)
CRC generation code
Watchdog timer implementation
Synchronous FIFO
Asynchronous FIFO
Memory implementation
example to showcase race condition using blocking assignments
system task usage: $display, $monitor, $strobe
PLI, VPI implementation
Memory controller RTL understanding, architecture understanding
Clock generation with Duty cycle & Jitter
Interrupt Controller
SPI Controller
I2C Controller
UART Controller

Course videos

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Lecture 1 Verilog for Design and Verification course overview, Assignment overview, Verilog code execution tools overview, Verilog evolution, Verilog Design Examples, Combinational Logic, Sequential Logic, Half Adder Modelling, Why Verilog is required?, How Verilog implements concept of time? Verilog code Execution stages, Why we need run simulation, Why Verilog is easy? How Verilog differs from other programming languages?, Verilog Abstraction styles. 03:00:13
Lecture 2 "Verilog literals, Differences between x & z? Setup time, Hold time, Types of nets, Vectors, Arrays, Differences between Vector & Array, Vector Assignments, Array Assignments, Different styles of Radix, Radix Conversions, Data Types(Integer, real, time), Array of Vectors, Simple Memory design coding Example, Test bench coding, Memory Parameters, Difference between test bench & test case, Waveforms Analysis" 03:17:19
Lecture 3 "Verilog Data types, Memory: Different ways of access(Front door access, Back door access),$readmemh, $value$plusargs, Procedural statements, Procedural blocks, Case statement, String data type declaration in Verilog, Memory Implementation(Design & Test bench)" 04:18:16
Lecture 4 Clock Generation, Why we need real data type in Verilog?, Event Scheduling, Simulator Regions, Frequency, Jitter, Duty Cycle, Skew, Time Scale, Time step, Time Precision, Verilog Operators. 03:32:52
Lecture 5 Verilog Abstraction Levels, Reg and wire data type declaration in Verilog test bench, Defining Macro, seed, Differences between $monitor and $display, Steps to write test bench for combinational logic. Memory Wrapper, Parameter, genvar, Multibit Full Adder, Memory Wrapper using generate, Different types of Connections for DUT Instance in TB(Connection by position, connection by name, default connection),generate, genvar, Parameter, Parameterizable Full Adder, Parameter overriding, Hierarchical Modeling." 03:37:52
Lecture 6 Initial block& always block, Blocking and Non-blocking, Synthesis examples, Continuous Assignments, Discrete Assignment, fork_join, fork_join practical significance, Concurrent and Sequential Execution of Code, Race Condition, FIFO, Asynchronous FIFO, Synchronous FIFO, Why do we need FIFO?, FIFO Detailed Functionality with Analogy, Steps for implementing code in any Project. 03:35:25
Lecture 7 Pipelining, FIFO Explanation with Analogy of Processor & Keyboard communicaton in SOC, Asynchronous FIFO, Synchronous FIFO, FIFO Coding, Importance FIFO signals(write, read, full, empty, error, wr_ptr, rd_ptr), Code for reading DEPTH number of locations from FIFO, Updating to FIFO code to Asynchronous FIFO code, Verilog Language Constructs 04:35:08
Lecture 8 Verilog Constructs, Differences between Synchronous and Asynchronous reset, Blocking and Non blocking Assignment, APB Protocol, Interrupt Protocol, SPI Controller 04:39:25
Lecture 9 Gray code counter(behavioral, gate level, switch level), Watchdog timer(1:42:47), Single port RAM, Dual Port RAM, table & endtable(Mux_2x1_primitive),TLC, Shift Register 03:19:25
Lecture 10 Traffic light controller, Parallel In Serial Out(PISO), SPI Protocol 04:02:39
Lecture 11 SPI Controller RTL coding and verification, I2C Protocol, I2C Controller RTL coding overview 03:22:14
Lecture 12 Watchdog timer, PLI implementation 02:46:52
Lecture 13 I2C Controller, PISO implementation 01:30:00
Lecture 14 CRC generation 0:25:30
Lecture 15 Verilog interview focused session 02:03:00


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